Is it (Finally) ESL’s Time?



By paul ~ January 9th, 2009. Filed under: Industry, Systems Engr..

I just read a very interesting whitepaper by Brian Bailey entitled System Level Virtual Prototyping becomes a reality with OVP donation from Imperas (PDF, registration & login may be required) which I found on the OVP World web site. This was published June, 2008, so please forgive me for being so slow to find it.

The paper is an excellent survey of some of the major ESL methods in use. It makes a strong argument for the OVP World approach and offerings. In addition, Brian points out some of the key drivers in the SoC industry that should be leading to faster adoption of ESL methods. Not surprisingly, one of these drivers is the continuing growth in SoC complexity and, in particular, the number of multi-processor SoCs.

In the Abstract, Brian observes:

For many years, Electronic System Level (ESL) design and verification has been on the cusp of widespread adoption, but never seems to get there. Universities and companies claim to have the necessary breakthrough only to see the technology sit there for years or the company to hobble along without ever really becoming a success. Is this because ESL is failing to deliver on the promises or that the products are flawed? Is it because the preconceived notion of ESL is wrong?

I share Brian’s perplexity. We share a little bit of history, Brian and I. Back in ’98, (wow, over a decade ago) we worked together on an ESL project that brought Mentor Graphics’ Seamless CVE tool together with Foresight to create a higher-level co-design solution. The result was pretty cool. You could build a high-level model of your system in Foresight, iron out the design issues and verify it. Then, when you had HDL and software, you could put them together in Seamless CVE and exercise the result from Foresight via co-simulation. The system-level model became the testbench for the implementation. We actually demonstrated this using the predecessor to the model described in the Digital Imaging with ARM whitepaper in the Mentor suite at the 2000 DAC.

The idea was well received, but the product wasn’t successful. I think we sold one seat of the combination. Nor were later developments that enabled Foresight co-simulation with HDL simulators successful. I have often wondered why…

Brian goes on to speculate that a key reason for the slow pace of ESL adoption is that, after about 10 years:

We have neither model interoperability nor independence between model and tool. Because of this, it is almost impossible to put together complete ESL flows today, and thus ESL adoption remains patchy at best, and often derided.

Maybe. While I think that interoperability will be a great enabler, I’m not sure that’s what the holdup has been. More fundamentally, I think that the commercial electronics design community does not adopt higher abstraction design approaches until they show an order of magnitude productivity improvement. For ESL (and above, where we sit) this has been difficult to prove and will likely always be difficult to prove conclusively. However, there comes a point, as Brian points out in the paper, where the sheer complexity of designs drives us to a higher level of abstraction. System-level modeling approaches have been used for years in the military/aerospace industries for this very reason. Perhaps SoC designs are now reaching this point.

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